In this study, we introduce a machine learning approach designed to augment the conventional Rigorous Coupled-Wave Analysis (RCWA) method used in scatterometry measurements. The utility of this approach is illustrated
through two practical examples. Initially, we applied it to a recess structure in trench MOSFET. Following the application of our machine learning method to the RCWA model, the recess depth measurement exhibited improved stability and
uniformity across the wafer. In the second example, we measured a 2D line trench in silicon (with a depth of 22 μm); here, both the top and bottom widths are parameters of interest.
We show that our machine learning based model is more robust compared to the conventional RCWA method. Our results were then cross-verified using atomic force microscopy results and cross-section Scanning Electron Microscopy data, respectively.

Topics: Machine learning, spectral reflectometry, scatterometry, trench shape, CD, OCD, RCWA, recess depth

The thickness of the chalcogenide ovonic threshold switching (OTS) layer is one of the most critical parameters for the switch-only memory (SOM) process control. Traditionally, the OTS thickness and composition were measured by XRF
using the amounts of Ge, As, and Se. Still, XRF has a few limitations in delivering the required performance, especially for products with multilayer memory architecture. For these products, X-ray fluorescence (XRF) signals overlap and
cannot be used to measure the thickness of each layer. In the current paper, we have studied three new alternative approaches for measurements of the OTS thickness on-cell: Spectral Interferometry, Raman spectroscopy, and Hybrid
Machine Learning technique. The first method, Spectral interferometry with the Vertical Traveling Scatterometry approach (VTS), allowed OCD modeling of the top of the structure by blocking the complex underlayers and measuring only the
top OTS thickness on all targets, including within the chip. The second method, Raman spectroscopy, demonstrated oncell dimensional capabilities with an excellent correlation of the Ge-Se, As-Se, and Ge-Ge bonds of Raman active
chalcogenide to TEM OTS thickness values. Finally, the third method used Raman parameters calibrated with TEM as a reference thickness for the ML solution using the VTS spectra on-cell. This ML method is fast, model-free, and requires
minimal TEM samples for setup. All three methods have demonstrated capability for on-cell measurements and HVM process control.

Keywords: OTS thickness, Chalcogenide, Spectral Interferometry, Raman Spectroscopy, Hybrid Machine Learning

This paper demonstrates the successful lab-to-fab transition of dynamic secondary-ion mass spectrometry (SIMS). In comparison to traditional lab SIMS, the in-line version is optimized for automated wafer and measurement sequence
handling and high throughput measurements in small areas. Key advantages are fast turn-around time, reduced scrap, increased yield, and the measured wafer can continue processing in the manufacturing line. The benefits of in-line SIMS
in the production environment are demonstrated for several use cases: matching and monitoring the long-term stability of epitaxy tools on monitor wafers, process optimization and monitoring of epitaxial Si and SiGe layers on blanket and patterned wafers with blanket metrology targets, measurement of implant and dopant profiles on blanket and patterned wafers, and characterization of the Ge and B diffusion in multi-layer stacks stimulated by high-temperature annealing.
Additionally, the characterization of the source/drain epitaxy in a fully integrated nanosheet gate-all-around transistor architecture is demonstrated and discussed. The results are compared to off-line lab SIMS and alternative methods where
available.
Keywords: In-line metrology, SIMS, gate-all-around, nanosheet, epitaxy, diffusion, dopant profiling, implant profiling

We have demonstrated the unique capabilities of spectral interferometry (SI) with vertical traveling scatterometry
algorithms (VTS) to solve 3D NAND challenges by measuring complex layer thicknesses of the multideck 3D
structures directly from the VTS signals, without modeling, with Cell Over Periphery (COP) underlayer filtering.
Multiple examples are presented in the paper, including the measurement of the thin and thick layers of memory
structures above the complex logic arrays and the remaining thickness of the fully processed Si wafer from the back
side after thinning.
In addition, VTS and AI enable direct profiling of the deep through-type cell metal contacts in the areas with
nonperiodic staircases and significant lateral variations under the measurement spot.
Keywords: OCD, Spectral Interferometry, Spectral Reflectometry, 3D NAND, HAR, contact hole profiles, staircases,
and non-periodical targets.

In the field of semiconductor manufacturing, Scanning Electron Microscope (SEM) is employed for critical dimension (CD) measurements, overlay measurements, and defect inspections to ensure the quality and reliability of semiconductor devices. Nevertheless, SEM images inherently carry a significant level of noise, leading to inaccurate metrology and false defect inspections. Therefore, it is crucial to develop denoising techniques. One widely used method is frame averaging, which reduces cumulative noise by averaging multiple scans. While increasing scan times enhances SEM image quality, it comes with drawbacks such as surface charging, pattern shrinkage, and reduced throughput. Deep learning (DL) techniques, including supervised and unsupervised approaches, have shown remarkable progress in the field of SEM image denoising. However, supervised methods are notably affected by phenomena such as pattern shrinkage and surface charging, which occur during the capture of reference images. On the other hand, unsupervised methods are typically more effective with lower noise levels. In this paper, we introduced a flexible DL method for denoising SEM images that operates without the requirement for paired data. To demonstrate its effectiveness, we analyzed and evaluated its performance in two metrology tasks. Experimental results validated the efficacy of our method in reducing noise, demonstrating its applicability to both ADI and AEI.

ABSTRACT
Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to
acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial
separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence
of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.
Keywords: Through-Silicon-Vias, Spectral Interferometry, Metrology